This invention relates to a semiconductor memory device.
There is a tendency for semiconductor memory devices of high integration, large capacity and multi function to increase steadily year by year. Especially, such a tendency is conspicuous in DRAMs (Dynamic Random Access Memories).
Moreover, in recent years, there have appeared semiconductor memory devices in which the number of bits of memory information is not equal to 2.sup.n, e.g., semiconductor memory devices of 9 bits or 18 bits, etc. Among such semiconductor memory devices, there is known a semiconductor memory device in which 8 bits of, e.g., 9 bits are used as memory information (this memory information of 8 bits will be refered to as "signal data" hereinafter), and the remaining one bit is used for detection of error. This error detection is generally called a parity check, and data used for such a parity check is generally called parity data.
Explanation will now be given in connection with such conventional semiconductor memory devices by taking as an example a DRAM having an input/output circuit configuration of 512K.times.9 bits.
FIG. 7 is a block diagram conceptually showing the configuration of such a DRAM.
The DRAM shown in this figure includes, in total, nine basic circuit blocks (n.sub.0 -n.sub.8 in the figure) called a circuit block In this DRAM, the core planes n.sub.0 -n.sub.7 are used for storing signal data, and the circuit blocks n.sub.8 is used for storing parity data.
The configuration of each of core planes n.sub.0 -n.sub.8 is schematically shown in FIG. 8.
As shown in this figure, a column decoder 3 is arranged between two memory cell groups 4 and 5, and row decoders 1 and 2 are respectively arranged on the upper end sides of the memory cell groups 4 and 5. The memory cell groups 4 and 5 respectively include memory cells of 256K bits, and further includes 256 word lines WL.sub.0 -WL.sub.255 and 1024 bit line pairs BL.sub.0 -BL.sub.1023 in correspondence with respective memory cells.
Between the column decoder 3 and the memory cell groups 4 and 5, wiring or interconnecting regions 6 and 7 are provided. These wiring regions 6 and 7 respectively include wirings (not shown) connecting the column decoder 3 and the bit wiring pairs BL.sub.0 -BL.sub.1023. Further, the wiring region 6 includes digit lines DQ.sub.1 and DQ.sub.2 for inputting/outputting data between the memory cell group 4 and the external. Similarly, the wiring region 7 includes digit lines DQ.sub.3 and DQ.sub.4 for inputting/outputting data between the memory cell group 5 and the external.
In carrying out data read or write operation with respect to the circuit blocks n.sub.0 -n.sub.8 of such a configuration, the row decoder 1 and 2 first selects arbitrary word lines WL.sub.0 -WL.sub.255, respectively. Simultaneously with this, the column decoder 3 selects two pairs at a time from the bit line pairs BL.sub.0 -BL.sub.1023 with respect to respective memory cell groups 4 and 5.
Thus, data of 2 bits are read out from the memory cell group 4 or are written thereinto through digit lines DQ.sub.1 and DQ.sub.2 at the same time. Similarly, data of 2 bits are read out from the memory cell group 5 or are written thereinto through digit lines DQ.sub.3 and DQ.sub.4 at the same time. Namely, data of 4 bits are read out from one circuit block or are written thereinto at the same time.
As stated above, this DRAM is constructed so that respective circuit blocks carry out a read or write operation of 4 bit data at the same time by using four digit lines DQ.sub.1 -DQ.sub.4.
In this instance, signal data of this DRAM is 8 bits as described above. Accordingly, two core planes are selected in carrying out a write operation of signal data, and write operations of signal data are carried out by 4 bits with respect to respective circuit blocks. Similarly, also in carrying out a read operation of signal data, two circuit blocks are selected, and read operations of signal data are carried out by 4 bits from respective circuit blocks.
The reason why a scheme is employed in which write or readout operations of signal data are respectively carried out by 4 bits with respect to two circuit blocks, in place of a scheme in which write or read operations of signal data, are carried out by 1 bit with respect to circuit blocks n.sub.0 -n.sub.7 for signal data, is to lessen the number of circuit blocks used at the same time, to thereby reducing power consumption.
In this instance, 4 bits of the first half of signal data of 8 bits are collectively stored into one of the circuit blocks n.sub.0 -n.sub.3. For this reason, as reference to FIG. 7 assists in understanding, input/output sections IO.sub.1 -IO.sub.4 of nine input/output sections IO.sub.1 -IO.sub.9 are connected to digit lines DQ.sub.1 -DQ.sub.4 of the circuit blocks n.sub.0 -n.sub.3, respectively. Similarly to the above, since 4 bits of the latter half are collectively stored into one of circuit blocks n.sub.4 -n.sub.7, input/output sections IO.sub.5 -IO.sub.8 are connected to digit lines DQ.sub.1 -DQ.sub.4 of the core planes n.sub.4 -n.sub.7, respectively. Further, since parity data are all stored into the circuit block n.sub.8, the input/output section IO.sub.9 for parity bits is always connected to any one of digit lines DQ.sub.1 -DQ.sub.4 of the circuit block n.sub.8. It is to be noted that, with respect to the input/output section IO.sub.9, a decoder for digit line (not shown) is further required in order to select only one of digit line pairs DQ.sub.1 -DQ.sub.4 of the circuit block n.sub.8.
As stated above, the combination of circuit blocks selected by one write/readout operation is one of the combination of n.sub.0, n.sub.4 and n.sub.8, the combination of n.sub.1, n.sub.5 and n.sub.8, the combination of n.sub.2, n.sub.6 and n.sub.8, and the combination of n.sub.3, n.sub.7 and n.sub.8.
The wiring configuration of bit line pairs in the case where circuit blocks n.sub.0, n.sub.4 and n.sub.8 are selected and are caused to be active is shown in FIGS. 9(a)-9(c).
With respect to the circuit blocks n.sub.0 and n.sub.4, arbitrary ones of output signals C.sub.0 -C.sub.511 from the column decoder 3 are respectively turned ON, and two word lines WL are further selected. Thus, memory cells are respectively selected by 2 bits from the left and right memory cell groups 4 and 5. Between the selected memory cells and respective input/output sections IO.sub.1 -IO.sub.8, transfer of signal data is carried out through digit line pairs DQ.sub.1 -DQ.sub.4.
Further, in the circuit block n.sub.8, only one digit line is selected by decoder for digit line (not shown) as described above. Accordingly, transfer of parity data is carried out with respect to only memory cell corresponding to the selected digit line of memory cells of 4 bits selected by four bit line pairs and two word lines.
However, such a conventional DRAM had the drawbacks described below.
(1) Since the conventional DRAM of this kind requires a circuit block n.sub.8 exclusively used for parity data as described above, row decoders 1 and 2 and column decoder 3 exclusively used for this circuit block are required, thereby increasing chip size.
(2) Since the wiring length is elongated as a result of the fact that the chip size is increased as stated above, the wiring capacitance and/or the wiring resistance is also greatly increased, constituting the cause of delay in the operation of the chip.
(3) While an approach is employed to reduce power consumption by allowing circuit blocks n.sub.0 -n.sub.7 for signal data to be basically operative, e.g., by only twos as described above, the circuit block n.sub.8 for parity data must be operated at all times. Accordingly, even if an attempt is made to carry out a divisional operation to thereby reduce current consumption of the device, the existence of the circuit blocks n.sub.8 exclusively used for parity data lessens the effect of such a reduction. Such a problem becomes more conspicuous as the capacity of DRAM the is increased.
(4) In addition, since the circuit block n.sub.8 for parity data is different from the circuit blocks n.sub.0 -n.sub.7 for signal data in the control method and the decoding method, a control circuit and/or a decode circuit which are exclusively used for the circuit block n.sub.8 are required. For this reason, the system became complicated and costly.